HIDE: A hardware intelligent description environment

This paper presents a logic-based structural hardware design environment, called HIDE, developed at the Queen’s University of Belfast. Central to this environment is a hardware description language which provides more abstract and elegant hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog. The guiding principle in designing HIDE was the satisfaction of the dual requirement of abstract hardware design and hardware efficiency. The paper presents several novel developments of earlier published work, including the detailed syntax, semantic and implementation of the latest version of HIDE. The latter includes 3D circuit composition, layout managers and higher level block constructors. Using a small set of powerful constructors, HIDE allows hardware designers to describe and assemble highly efficient circuits from high level geometrical descriptions based on Signal Flow Graphs (SFG). Optimised hardware is generated automatically from such descriptions in the form of fully placed configurations in EDIF format, or VHDL. The paper illustrates this in the construction of a high performance Matrix-Multiplier core for Xilinx Virtex FPGAs. Comparative implementation results are presented which show that our HIDE system matches the performance (in terms of speed and area) of specialised FPGA vendor tools such as the Xilinx Core Generator, with the added feature of being a full programming environment. A qualitative comparison of the HIDE language with other hardware design languages, namely: the industry standard VHDL and a hardware design language similar to HIDE, called LAVA, shows several merits of HIDE and outlines future development plans.